DDR4 memory organization and how it affects memory bandwidth

What this post added

This post details the concepts of memory rank and organization in DDR4 memory modules, explaining how they affect memory bandwidth. It defines memory rank as sets of DRAM chips on a module (single, dual, quad) and discusses rank interleaving. It also explains memory depth and width, illustrating how x4, x8, and x16 device widths contribute to chip capacity. Finally, it explores the relationship between page sizes and timing parameters like tFAW, demonstrating how these hardware specifics influence performance.