Debugging Hardware Performance on Gen X Servers

This post details the debugging process for performance discrepancies observed in Gen X AMD EPYC Zen 2 (Rome) servers. The investigation involved using DGEMM to assess CPU performance and TDP, iPerf for network bottlenecks, and the AMD HSMP tool. The root cause identified was a mismatch between the memory clock frequency (1467 MHz) and the Infinity Fabric clock frequency (1333 MHz). A vendor-provided BIOS update that set the Infinity Fabric clock to 1467 MHz resolved the performance delta, bringing SKU-B servers to parity with SKU-A.