Describe model-to-GPU execution pipeline
Describe Model-to-GPU Execution Pipeline
You are asked to explain the end-to-end path a machine learning model takes from authoring to high-performance inference on a GPU. Walk through the stages below and describe what happens at each step:
- Frontend representation: How a model is defined in a high-level framework (e.g., dynamic vs. static graphs, tracing vs. scripting).
- Export to an intermediate representation (IR): Exporting to ONNX or a similar IR; making shapes/layouts explicit; simplifying the graph.
- Compilation to device code: Lowering from IR to kernel calls or device code; scheduling; autotuning; static vs. dynamic shapes.
- Runtime execution: Memory management, kernel launch, streams, batching, and handling dynamic inputs.
Then, discuss common compiler/runtime optimization techniques and their trade-offs, including:
- Kernel/operator fusion
- Quantization (e.g., INT8, FP16/FP8)
- Operator specialization and autotuning
- Layout and precision selection
- Memory planning and graph partitioning
Finally, contrast considerations for data-center versus edge hardware targets:
- Throughput vs. latency priorities
- Batch size, power/thermal limits, memory budgets
- JIT vs. AOT, startup time, binary size, determinism
Assume a modern GPU software stack with an IR (e.g., ONNX/MLIR/Relay/XLA), a compiler/runtime (e.g., ONNX Runtime, vendor-specific runtimes), and access to common math libraries (e.g., BLAS/DNN). Keep your explanation structured and concise.
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Core dilemma
Balancing the complexity of ML model representation and compilation with the need for highly optimized, low-latency execution on diverse GPU hardware.
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Describe model-to-GPU execution pipeline
Describe Model-to-GPU Execution Pipeline
You are asked to explain the end-to-end path a machine learning model takes from authoring to high-performance inference on a GPU. Walk through the stages below and describe what happens at each step:
- Frontend representation: How a model is defined in a high-level framework (e.g., dynamic vs. static graphs, tracing vs. scripting).
- Export to an intermediate representation (IR): Exporting to ONNX or a similar IR; making shapes/layouts explicit; simplifying the graph.
- Compilation to device code: Lowering from IR to kernel calls or device code; scheduling; autotuning; static vs. dynamic shapes.
- Runtime execution: Memory management, kernel launch, streams, batching, and handling dynamic inputs.
Then, discuss common compiler/runtime optimization techniques and their trade-offs, including:
- Kernel/operator fusion
- Quantization (e.g., INT8, FP16/FP8)
- Operator specialization and autotuning
- Layout and precision selection
- Memory planning and graph partitioning
Finally, contrast considerations for data-center versus edge hardware targets:
- Throughput vs. latency priorities
- Batch size, power/thermal limits, memory budgets
- JIT vs. AOT, startup time, binary size, determinism
Assume a modern GPU software stack with an IR (e.g., ONNX/MLIR/Relay/XLA), a compiler/runtime (e.g., ONNX Runtime, vendor-specific runtimes), and access to common math libraries (e.g., BLAS/DNN). Keep your explanation structured and concise.