Branch predictor: How many "if"s are too many? Including x86 and M1 benchmarks!

This post delves into the performance implications of branch prediction, specifically analyzing the cost of numerous conditional and unconditional branches within performance-critical code. It provides theoretical background on branch predictors (BPUs) and the Branch Target Buffer (BTB), and presents experimental results on AMD EPYC and Apple M1 processors. The findings highlight that the number of branches and their density significantly impact performance, with a noticeable degradation beyond a certain threshold (around 4096 branches) due to BTB limitations and potential cache misses. This contributes to the understanding of low-level hardware performance optimization.