TechPrufer
Get started
Jane Street
Jane Street logoJane Street · Feature trail

ASIC Reverse Engineering Puzzle

2 posts · Aug 2026 – Oct 2026

What this trail covers

This post extends the ASIC reverse engineering puzzle capability by revealing the solution to the puzzle and detailing the various methods solvers used to reverse-engineer the chip. It highlights techniques such as netlist extraction from GDS layout, simulation using cell models or custom evaluators, logical analysis of circuit modules, dynamic signal exploration, and SAT solving. The post also details the chip's functionality as a hardware checker for an 11x11 Star Battle puzzle and discusses the obfuscation used in the output generator.

All Jane Street trails
  1. Results from the ASIC puzzleThis post details the solution to the ASIC reverse engineering puzzle, which was a hardware checker for an 11x11 Star Battle puzzle. It describes the chip's parallel checks for row, column, and region star counts, adjacency constraints, and total star count. The post also elaborates on the output generator's obfuscation mechanism using an LFSR and the deobfuscation process. It further categorizes and explains the diverse approaches taken by solvers, including netlist extraction, simulation, logical walkthroughs, dynamic exploration, and SAT solving, providing examples of specific techniques and tools used.
  2. Can you reverse engineer an ASIC?This post introduces a novel ASIC reverse engineering puzzle, providing a GDS file of a chip and sample inputs/outputs. It guides participants through the process of recovering a netlist from the layout, understanding the circuit's purpose, and ultimately finding a hidden string value. It also includes a warm-up example with a binary adder and mentions future challenges involving designing and fabricating custom chips.