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Hardware Design Testing

8 posts · May 2020 – Sep 2026

What this trail covers

This post extends the hardware design testing discussion by introducing a competition to design an open-source, general-purpose protocol emulator ASIC. It details the technical approach of designing a reprogrammable chip to support new protocols after fabrication, aiming to foster skills in hardware analysis and design exploration. This capability extends to adapting the programming language to better support proof-oriented techniques and integrating with external formal methods tools.

All Jane Street trails
  1. Can you design a chip? Announcing the protocol emulator ASIC competitionThis post announces a competition to design a general-purpose protocol emulator ASIC. It outlines the challenge of creating a reprogrammable chip that can emulate various hardware protocols (UART, SPI, I2C, with stretch goals for USB and Ethernet) using a small CPU with a custom instruction set. It references existing concepts like RP2040 PIO and TI PRU cores, and encourages the use of Hardcaml, formal methods, and AI-assisted verification. The post also details the process, rules, and constraints for submitting designs to Tiny Tapeout.
  2. Advent of HardcamlThis post introduces Hardcaml, an OCaml library for hardware design, and demonstrates its use in conjunction with ASCII waveforms for testing hardware designs. It details the technical approach of generating and interpreting these waveforms within the Hardcaml framework, providing a human-readable format for test results that aids in debugging and verification of hardware designs.
  3. Accelerating zk-SNARKs - MSM and NTT algorithms on FPGAs with HardcamlThis post introduces the acceleration of zk-SNARKs (MSM and NTT algorithms) on FPGAs using Hardcaml, detailing the technical approach and its benefits for hardware acceleration.
  4. Growing the Hardcaml toolsetThis post introduces new capabilities to the Hardcaml toolset, focusing on testing hardware designs. It details the technical approach for using ASCII waveforms to represent and test hardware signals, contributing to more robust hardware development.
  5. Using ASCII waveforms to test hardware designsIntroduces the use of ASCII waveforms as a method for testing hardware designs, providing a human-readable representation of test signals and results to aid in debugging and verification.